Abstract: The postquantum cryptographic algorithm MLKEM has emerged as a key standard for resisting quantum computing attacks, and its highspeed hardware implementation is crucial for future network security. This paper proposes a hardware architecture for MLKEM and optimizes several specific modules within the design. For the encoding and decoding operations, FIFObased processing is employed to reduce resource consumption. In addition, the compression operation is analyzed to eliminate division operations during the compression process, and division and rounding are combined through specific parameter selection. Furthermore, a compact operation schedule is adopted to increase parallelism while reducing the overall computation latency. The proposed design is implemented and synthesized on a Xilinx Artix7 platform. Experimental results show that the maximum operating frequency reaches 125MHz, with resource utilization of 19791 LUTs, 8364 FFs, 22 BRAMs, and 9 DSPs. Under three security levels, the latencies of key generation, encapsulation, and decapsulation are 354149576593 cycles, 404255047183 cycles, and 6822907211274 cycles, respectively. The proposed architecture achieves a favorable balance between resource overhead and computational performance.

Key words: postquantum cryptography, MLKEM, Kyber, hardware acceleration, polynomial arithmetic

摘要： 格基密钥封装机制(module latticebased key encapsulation mechanismm, MLKEM)已成为抵御量子计算攻击的关键标准，其高速硬件实现对于未来网络安全至关重要.提出了一种MLKEM硬件架构，并对其中的特定模块进行了优化.使用FIFO进行编解码操作，减少了资源消耗.同时，还对压缩运算进行了分析，避免了压缩过程中的除法运算，并通过特定的参数选择将除法与舍入操作合并进行.最后，对操作时序进行了紧凑安排，在提高并行度的同时缩短了整体运算时间.在Xilinx Artix7平台上进行了实验.结果表明，最高运行频率为125MHz，资源消耗为19791个LUT、8364个FF、22个BRAM和9个DSP，3种安全强度下密钥生成、封装与解封装操作的延迟分别为354149576593时钟周期、404255047183时钟周期和6822907211274时钟周期，在资源开销与运算速度之间取得了较好平衡.

关键词: 后量子密码, MLKEM, Kyber, 硬件加速, 多项式运算