[1]鲍聪颖, 吴昊, 陆凯, 等. 基于可信执行环境的5G边缘计算安全研究[J]. 信息安全研究, 2023, 9(1): 3847[2]Xia Ke, Luo Yukui, Xu Xiaolin, et al. SGXFPGA: Trusted execution environment for CPUFPGA heterogeneous architecture[C] Proc of DAC Conference. Piscataway, NJ: IEEE, 2015: 301306[3]Liang Hongliang, Li Mingyu, Chen Yixiu, et al. Establishing trusted IO paths for SGX client systems with aurora[J]. IEEE Trans on Information Forensics and Security, 2020, 15(1): 15891600[4]Zhang Yiming, Hu Yuxin, Ning Zhenyu, et al. SHELTER: Extending arm CCA with isolation in user space[C] Proc of USENIX Security Symposium Conference. Berkeley, CA: USENIX Association, 2023: 62576274[5]Costan V, Lebedev I, Devadas S. Sanctum: Minimal hardware extensions for strong software isolation[C] Proc of USENIX Security Symposium Conference. Berkeley, CA: USENIX Association, 2016: 857874[6]Bourgeat T, Lebedev I, Wright A, et al. MI6: Secure enclaves in a speculative outoforder processor[C] Proc of MICRO Conference. New York: ACM, 2019: 4256[7]Lee D, Kohlbrenner D, Shinde S, et al. Keystone: An open framework for architecting trusted execution environments[C] Proc of EuroSys Conference. New York: ACM, 2020: 116[8]Feng Erhu, Lu Xu, Du Dong, et al. Scalable memory protection in the PENGLAI enclave[C] Proc of USENIX OSDI Symposium Conference. Berkeley, CA: USENIX, 2021: 275294[9]Weiser S, Werner M, Brasser F, et al. TIMBERV: Tagisolated memory bringing finegrained enclaves to RISCV[C] Proc of NDSS Conference. Virginia, Alexandria: ISOC, 2019[10]Hoang T T, Duran C, Serrano R, et al. Trusted execution environment hardware by isolated heterogeneous architecture for key scheduling[J].IEEE Access, 2022, 10: 460144602710[11]Nasahl P, Schilling R, Werner M, et al. HECTORV: A heterogeneous CPU architecture for a secure RISCV execution environment[C] Proc of ASIA CCS Conference. New York: ACM, 2021: 187199[12]Ma Jun, Chong Ting, Li Lei, et al. Construction of RISCV lightweight trusted execution environment based on hardware extension[C] Proc of ICPICS Conference. Piscataway, NJ: IEEE, 2021: 237242[13]RISCV IOPMP Task Group. RISCV IOPMP architecture specification[ROL]. 2023 [20240801]. https:lists.riscv.orggtechiopmpattachment34710iopmpv0.9.2RC3.pdf[14]Chen yuehai, Chen Huarun, Chen Shaozhen, et al. DITES: A lightweight and flexible dualcore isolated trusted execution SoC based on RISCV[J]. Sensors, 2022, 22(16): 59815981
|